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16 Mbit LPC Serial Flash
A Microchip Technology Company
SST49LF016C
Data Sheet
Write Protect / Top Block Lock
The Top Boot Lock (TBL#) and Write Protect (WP#/AAI) pins are provided for hardware write protec-
tion of device memory in the SST49LF016C. The TBL# pin is used to write protect 16 KByte at the
highest memory address range for the SST49LF016C. WP#/AAI pin write protects the remaining sec-
tors in the flash memory. An active low signal at the TBL# pin prevents Program and Erase operations
of the top Boot Block. When TBL# pin is held high, write protection of the top Boot Block is then deter-
mined by the Boot Block Locking registers. The WP#/AAI pin serves the same function for the remain-
ing sectors of the device memory. The TBL# and WP#/AAI pins write protection functions operate
independently of one another. Both TBL# and WP#/AAI pins must be set to their required protection
states prior to starting a Program or Erase operation. A logic level change occurring at the TBL# or
WP#/AAI pin during a Program or Erase operation could cause unpredictable results. TBL# and WP#/
AAI pins cannot be left unconnected.
TBL# is internally OR’ed with the top Boot Block Locking register. When TBL# is low, the top Boot
Block is hardware write protected regardless of the state of the Write-Lock bit for the Boot Block Lock-
ing register. Clearing the Write-Protect bit in the register when TBL# is low will have no functional
effect, even though the register may indicate that the block is no longer locked.
WP#/AAI is internally OR’ed with the Block Locking register. When WP#/AAI is low, the blocks are
hardware write protected regardless of the state of the Write-Lock bit for the corresponding Block
Locking registers. Clearing the Write-Protect bit in any register when WP#/AAI is low will have no func-
tional effect, even though the register may indicate that the block is no longer locked.
AAI Enable
The AAI Enable pin (WP#/AAI) is used to enable the Auto Address Increment (AAI) mode. When the
WP#/AAI pin is set to the Supervoltage V H (9±0.5V), the device is in AAI mode with Multi-Byte pro-
gramming. When the WP#/AAI pin is brought to V IL /V IH levels, the device returns to LPC mode.
Ready/Busy
The Ready/Busy pin (RY/BY#), is an open drain output which indicates the device is ready to accept
data in an AAI mode, or that the internal programming cycle is complete. The pin is used in conjunction
with the LD# pin to switch between these two flag states (see Table 18).
Load Enable
The Load Enable pin (LD#), is an input pin which when low, indicates the host is loading data in an AAI
programming cycle. Data is loaded in the SST49LF016C at the rising edge of the clock. If LD# is high,
it signals the AAI interface that the host is terminating the command. LD# low/high switches the RY/
BY# output from buffer free flag to programming complete flag (see Table 18).
No Connection (NC)
These pins are not connected internally.
?2011 Silicon Storage Technology, Inc.
9
DS25029A
06/11
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